DocumentCode
251980
Title
Transistor doping profile optimization for low power subthreshold circuits
Author
Hossain, M. Mofazzal ; Chowdhury, Mazharul Huq
Author_Institution
Comput. Sci. & Electr. Eng, Univ. of Missouri - Kansas City, Kansas City, MO, USA
fYear
2014
fDate
3-6 Aug. 2014
Firstpage
33
Lastpage
36
Abstract
Conventional device uses the halo and retrograde doping profiles to minimize short channel effect, body punch through, drain induced barrier lowering (DIBL) and variation of the threshold voltage. Also scaled non-uniform doping profile is required for super-threshold circuit to provide better control of the electrical characteristics of the device. Devices for subthreshold circuits do not require halo and retrograde doping profiles. This will reduce the number of steps in the fabrication process, parasitic capacitance and substrate noise dramatically. This paper introduces a new three-dimensional doping scheme for the transistors in subthreshold circuits. It is characterized by the absence of halos at the source and drain region. Under the proposed scheme there can be four different doping profiles for subthreshold device. In this paper we concentrate on Gaussian doping distributions both along the channel and across the depth of the transistor. Results show that the optimized device with the proposed doping profile improves the ON current. The analysis is done by varying the doping profile and gate-source voltage (Vgs), and the observations are compared with the super-threshold device.
Keywords
Gaussian distribution; circuit optimisation; low-power electronics; power integrated circuits; semiconductor doping; transistor circuits; DIBL; Gaussian doping distributions; body punch through; drain induced barrier lowering; drain region; electrical characteristics; fabrication process; gate-source voltage; halo doping profiles; low power subthreshold circuits; parasitic capacitance; retrograde doping profiles; scaled nonuniform doping profile; short channel effect minimization; source region; substrate noise; super-threshold circuit; three-dimensional doping scheme; threshold voltage variation; transistor doping profile optimization; Doping profiles; Junctions; Logic gates; Performance evaluation; Threshold voltage; Subthreshold and super-threshold operations; doping profile optimization; halo and retrograde doping; ultra-low-power design;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location
College Station, TX
ISSN
1548-3746
Print_ISBN
978-1-4799-4134-6
Type
conf
DOI
10.1109/MWSCAS.2014.6908345
Filename
6908345
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