Investigation of ESD Performance in Silicon Integrated Passive Devices

ESD failure limits have been measured in a variety of silicon integrated passive devices using the Human Body Discharge Model. The failure mechanism for these circuits is typically the destructive breakdown of the thin insulator layer in metal-insulator-metal capacitors. The capacitors in this particular technology have a static breakdown of 70 to 100 V. Failure from ESD events for a single capacitor typically occurs for voltages of 200 to 300 V. Tests of more complex circuits show that the ESD performance is extended by using series arrangements of capacitors. In some circuit types it is possible to use inductive shunt protection. This has been found to increase the failure voltage to above 3KV, which was the limit of the test equipment.