Joint-PDF of timing and power of nano-scaled CMOS digital gates due to channel length variation

This paper presents a method for estimating the joint parametric yield accurately. The statistical yield estimation approach predicts the joint probability distribution function (JPDF) of the gate performance (delay) and power (leakage) considering the channel length variation. This method is applied to primitive gates (NOT, NAND and NOR). To increase the model accuracy, a quadratic relationship between the threshold voltage and the channel length is considered. The relation includes the stacking effect for stacked transistors in complex gates such as NOR and NAND. To assess the accuracy of the approach, its yield estimation results are compared with those of the Monte Carlo simulations. The comparison reveals a very high accuracy with errors less than 3.7% for a 32 nm standard CMOS technology. In addition to the channel length variation, the technique may be extended to the variations of other parameters including temperature, supply voltage, and dopant fluctuation.