DocumentCode
252091
Title
Reduction in the area of a high voltage multiplexer
Author
Thirunakkarasu, Shankar ; Seymour, Robert E.
Author_Institution
Broadcom Corp., Austin, TX, USA
fYear
2014
fDate
3-6 Aug. 2014
Firstpage
282
Lastpage
285
Abstract
A high-voltage 16-channel, 16-bit settling, multiplexer is proposed with reduced area and better Total Harmonic Distortion (THD) and Crosstalk. Every conducting switch in this multiplexer is capable of handling +/-12V input with a constant low resistance across the entire input voltage range using a boosted-gate technique with +/-15V power supply to have better THD. The proposed multiplexer is simulated using 0.6um high-voltage thick-gate CMOS technology and verified through extensive spectre simulations. Layout was drawn and back-annotated simulations were done to verify its working.
Keywords
CMOS analogue integrated circuits; crosstalk; harmonic distortion; THD; back-annotated simulation; boosted-gate technique; constant low-resistance; crosstalk; high-voltage multiplexer; high-voltage thick-gate CMOS technology; size 0.6 mum; total harmonic distortion; word length 16 bit; Capacitors; Crosstalk; Logic gates; Multiplexing; Resistance; Switches; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location
College Station, TX
ISSN
1548-3746
Print_ISBN
978-1-4799-4134-6
Type
conf
DOI
10.1109/MWSCAS.2014.6908407
Filename
6908407
Link To Document