Design techniques for external capacitor-less LDOs with high PSR over wide frequency range

Author

Chang-Joon Park ; Silva-Martinez, Jose ; Onabajo, Marvin

Author_Institution

Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

342

Lastpage

345

Abstract

The paths for power supply noise leakage in low drop-out (LDO) voltage regulators are analyzed, and techniques are discussed to minimize their effects on the output voltage. An internally compensated high power supply rejection (PSR) LDO voltage regulator with adaptive supply noise compensation scheme is presented. Its regulated output voltage is 1.6 V to provide 0-50 mA of current with a power supply of 1.8 V. The measured PSR is better than -50 dB up to 4 MHz. The fabricated LDO occupies 0.25 mm² in a 0.18 μm CMOS technology. It consumes 80 μA of ground current. The load regulation for a 50 mA step with 100 ns rise/fall times is 200 mV.

Keywords

CMOS integrated circuits; circuit noise; power supply circuits; voltage regulators; PSR LDO voltage regulator; adaptive supply noise compensation scheme; current 0 mA to 50 mA; current 80 muA; design techniques; external capacitor-less LDOs; high PSR; internally compensated high power supply rejection; low drop-out voltage regulators; output voltage; power supply noise leakage; size 0.18 mum; time 100 ns; voltage 1.6 V; voltage 200 mV; wide frequency range; Capacitors; Logic gates; Noise; Power supplies; Regulators; System-on-chip; Transistors; Low drop-out (LDO); external capacitor-less LDO; power management; power supply rejection (PSR); system-on-chip (SoC);

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908422

Filename

6908422