A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm

This paper describes a fast-settling all-digital PLL with a low-power TDC based on retimed reference clock and a lock detector focused on monitoring a toggling phase error. With the intention of reducing power dissipation, the proposed TDC employs the low-rate reference (CKf_ref) and retimed reference (CKf_ros) clocks to measure the fine fractional phase error between the low-rate reference (CKf_ref) and high-rate oscillator (CKf_osc) clocks. In addition, the use of the retimed reference clock to the TDC results in a new simple DCO clock period (T_V) calculation algorithm which employs the maximum and minimum values for the fractional error correction (ε). A lock detector, which is required to accomplish the switchover of the DCO frequency tuning mode, allows a fast settling to be actuated independent of loop bandwidth and frequency step. By dissipating 8mW at 1.2-V supply voltage, the proposed digital PLL achieves 230ns settling time, 1.7ps_rms period jitter.