Fault models and compact test vectors for MOS opamp circuits

Analog VLSI technology processes are reaching matureness; nevertheless, there is a big constraint, regarding their use on complex electronic products: “the test”. The “Design for Testability” paradigms were developed to permit the test plan implementation early on in the design cycle. However to succeed in this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable for fault simulation on opamps, we propose in this work a methodology for functional fault modeling, and a method for test pattern generation. A fault dictionary for opamps is built and a procedure for compact test vector construction is proposed. Preliminary results have shown that high level opamp requirements, such as slew-rate, common mode rejection ratio etc, can be checked by this approach with good compromise among the fault modeling problems, the analog nature of the circuit and the circuit complexity by itself: