Pipeline-efficient hybrid vectoring implementation

Silicon area, power consumption and pipeline-efficiency are investigated for hardware implementations of a Cartesian-to-polar (i.e. both magnitude and phase) coordinate transformer (C2P). A novel hybrid scheme, consisting of both look-up and algorithmic constituents, is proposed, based on the VECTORING mode of the COordinate Rotation DIgital Computer (CORDIC) hardware algorithm, preceded by a principal axes transformation algorithm-derived look-up scheme. The iterative CORDIC algorithm is rigorous for infinite bit resolution, permitting in principle arbitrary precision, while its intrinsic sequential nature entails a substantial pipeline latency, and a high resolution overhead to combat finite iteration quantization error accumulation. Look-Up Table (LUT) size, due to the two Cartesian input dimensionality, increases rapidly with resolution and is thus limited to a small-resolution input data regime. Signal latencies may become essential e.g. for C2P inside a feedback loop. With the present hybrid scheme, numbers of iterations may be reduced by up to 50%, at no penalty or even at a reduction of silicon area and power consumption. Finally, such a hybrid architecture permits technology independent HDL models, a prerequisite for full portability and reuse.