Trace-Driven Performance Estimation of multi-core platforms

In hardware/software co-design for a multi-core platform, a crucial role is played by fast and accurate early performance estimation. One type of such estimation that is as fast as native simulation, cycle-approximate and applicable to both software and custom hardware is Transaction Level Model (TLM) Estimation that depends on TLM simulation. For every platform selection and mapping, however, the entire platform must be simulated. The simulation overhead is reduced by Trace-driven estimation but such estimation is not applicable to custom hardware and often requires Cycle Accurate Models (CAMs), which may not available for the whole platform. In this paper, we present Trace-Driven Performance Estimation (TDPE) of multi-core designs. TDPE is a trace-driven estimation but applicable to both software and hardware and requires no CAM. Since TDPE includes a mere single functional simulation, it is orders of magnitude faster than TLM Estimation. TLM Estimation is cycle-approximate by considering the data path of each Processing Element (PE), memory hierarchy, RTOS scheduling and overheads, bus arbitration and overhead. TDPE takes all of them into account so is as accurate as TLM Estimation.