LMS-based digital background linearization technique for VCO-based delta-sigma ADC

This paper presents a digital background linearization technique for VCO-based delta-sigma ADC. The nonlinearity of the VCO in the main ADC is mitigated with the aid of the reference OP-based delta-sigma ADC and the digital least-mean square (LMS) correction algorithm. The reference ADC provides sufficient linearity performance as the calibration reference to form an inverse transfer function of the nonlinear voltage-to-frequency characteristic while the LMS-based calibration scheme shortens the correction time to reduce energy consumption. The simulated SFDR/SNDR of 70.2 dB/62.7 dB over a bandwidth of 10 MHz is achieved, which is 23.3 dB/16.6 dB better than the SFDR/SNDR of uncalibrated ADC. A prototype first-order VCO-based ADC is designed in 90-nm CMOS process and dissipates 2.89 mW from a supply voltage of 1.2 V.