Title :
Monolithic 3D integration in a CMOS process flow
Author :
Fitzgerald, E.A. ; Yoon, S.F. ; Tan, C.S. ; Palacios, T. ; Zhou, X. ; Peh, L.S. ; Boon, C.C. ; Kohen, D.A. ; Lee, K.H. ; Liu, Z.H. ; Choi, P.
Author_Institution :
Low Energy Electron. Syst., SMART, Singapore, Singapore
Abstract :
We describe a 3D integration process flow in which the vertical distance from the CMOS layer to the novel device layer is 100-1000 nm. This short distance effectively defines the process flow as a silicon CMOS process flow and allows for the use of silicon infrastructure in process and design. Progress has been made in demonstrating various pieces of III-V device integration into a foundry 0.18 μm process on 200 mm wafers.
Keywords :
CMOS integrated circuits; III-V semiconductors; monolithic integrated circuits; silicon; three-dimensional integrated circuits; III-V device integration; Si; complementary metal oxide semiconductor; distance 100 nm to 1000 nm; monolithic 3D integration process; silicon CMOS process flow; size 0.18 mum; size 200 mm; CMOS integrated circuits; Foundries; Gallium nitride; HEMTs; Silicon; Substrates; Three-dimensional displays; 3D; CMOS; GaN; HEMT; III–V; InGaAs; LED; integration;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028197
