A new statistical setup and hold time definition

Author

Bai, Xiaoliang ; Patel, Prayag ; Zhang, Xiaonan

Author_Institution

Qualcomm Inc., San Diego, CA, USA

fYear

2012

fDate

May 30 2012-June 1 2012

Firstpage

1

Lastpage

4

Abstract

Process variability becomes prominent for circuits using nanometer manufacturing technology. With aggressive voltage scaling, unexpected failures occur due to excessive timing variation. Yield, number of components, and process variability are intrinsically linked. In this paper, we study the setup and hold time definition, margin, and characterization methodology. A new statistical margin quantifying methodology, setup and hold time definition and characterization methodology are proposed.

Keywords

nanoelectronics; power aware computing; statistical analysis; timing; characterization methodology; hold time definition; nanometer manufacturing technology; process variability; statistical margin quantifying methodology; statistical setup; timing variation; unexpected failures; voltage scaling; Clocks; Couplings; Delay; Flip-flops; Monte Carlo methods; System-on-a-chip; Flip-Flop; Monte-Carlo simulation; Process Local Variability; Setup Time and Hold Time margin; Statistical Timing Analysis; characterization and definition;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2012 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

pending

Print_ISBN

978-1-4673-0146-6

Electronic_ISBN

pending

Type

conf

DOI

10.1109/ICICDT.2012.6232837

Filename

6232837