18 ps ECL-gate delay in laterally scaled 30 GHz bipolar transistors

Author

Pruijmboom, A. ; Timmering, C.E. ; Hageraats, J.J.E.M.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

825

Lastpage

828

Abstract

ECL-gate delays as low as 18 ps have been achieved in conventional bipolar technology, with a cut-off frequency f/sub T/ of 30 GHz. Rather than optimizing vertical doping profiles for maximum f/sub T/, the transistors were optimized for high-speed circuit performance by reducing device parasitics. This simplifies their integration in BICMOS processes and, since lower f/sub T/s are achieved at lower current densities, allows a decreased power consumption for high-speed circuits. In this transistor technology a DC-coupled broad-band amplifier (BBA), with a record bandwidth of 11.7 GHz for 15 Gbit/s optical data links has been fabricated.<>

Keywords

BiCMOS integrated circuits; current density; delays; doping profiles; microwave bipolar transistors; semiconductor technology; 11.7 GHz; 15 Gbit/s; 15 Gbit/s optical data links; 18 ps; 30 GHz; 30 GHz bipolar transistors; BICMOS processes; DC-coupled broad-band amplifier; ECL-gate delay; conventional bipolar technology; cut-off frequency; device parasitics; high-speed circuit performance; high-speed circuits; laterally scaled; lower current densities; microwave transistors; power consumption; record bandwidth; transistor technology; vertical doping profiles; BiCMOS integrated circuits; Bipolar transistors; Circuit optimization; Current density; Cutoff frequency; Delay; Doping profiles; Energy consumption; Optical amplifiers; Semiconductor optical amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383297

Filename

383297