Multi-stage pulse shrinking time-to-digital converter for time interval measurements

This paper presents a new structure of pulse shrinking time-to-digital converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 mum CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as phase detector for phase locked loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.