DocumentCode
2525576
Title
A comprehensive approach to the partial scan problem using implicit state enumeration
Author
Kalla, Priyank ; Ciesielski, Maciej J.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
1998
fDate
18-23 Oct 1998
Firstpage
651
Lastpage
657
Abstract
This paper presents a novel technique and a practical algorithm for the selection of state registers for partial scan. Our model uses implicit techniques for FSM traversal to identify non-controllable state registers. Non-controllability of registers is evaluated by a systematic analysis of the state transitions and the encoding of the underlying FSM. By using our approach, we can not only identify non-controllable and difficult-to-control flip-flops, but also exploit the information of the unreachable states to judiciously select the minimum number of scan registers for high fault coverage. The effectiveness of our technique is illustrated over a large set of MCNC and ISCAS benchmarks. The results demonstrate the superiority of our method over conventional state-of-the-art scan register selection techniques in terms of higher fault coverage achieved by selecting fewer partial scan registers
Keywords
fault diagnosis; finite state machines; flip-flops; logic testing; performance evaluation; shift registers; FSM traversal; ISCAS benchmarks; MCNC; SIMPSON algorithm; effectiveness; encoding; fault coverage; finite state machine; flip-flops; implicit state enumeration; noncontrollable state registers; partial scan; partial scan registers; scan register selection; state registers; state transitions; systematic analysis; Automatic testing; Circuit faults; Circuit testing; Controllability; Costs; Flip-flops; Pattern analysis; Registers; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743209
Filename
743209
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