Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arrays

Author

Shamanna, Guru ; Gaurav, Raja ; Raghavendra, Y.K. ; Marfatia, Percy ; Kshatri, Bhunesh

Author_Institution

Intel Corp., Bangalore, India

fYear

2012

fDate

May 30 2012-June 1 2012

Firstpage

1

Lastpage

4

Abstract

VMIN induced Yield Loss is increasing in nanoscale CMOS era, due to quest for performance at low power. SRAM arrays are the largest contributor to this variety of yield loss due to a wide VMIN distribution. To minimize yield loss due to wide SRAM VMIN distribution, authors propose the use of error correction techniques and redundancy. Measured VMIN distribution data of a 30MB SRAM array designed in 32nm process technology node is presented to demonstrate efficacy of redundancy and error correction techniques.

Keywords

CMOS memory circuits; SRAM chips; error correction codes; nanoelectronics; nanostructured materials; redundancy; 6T SRAM arrays; ECC; SRAM VMIN distribution; VMIN distribution data; VMIN induced yield loss; error correction techniques; memory size 30 MByte; nanoscale CMOS; process technology node; redundancy; size 32 nm; Arrays; Error correction codes; Manufacturing; Program processors; Random access memory; Redundancy; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2012 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

pending

Print_ISBN

978-1-4673-0146-6

Electronic_ISBN

pending

Type

conf

DOI

10.1109/ICICDT.2012.6232861

Filename

6232861