Test methodology for a microprocessor with partial scan

Author

Day, Leland L. ; Ganfield, Paul A. ; Rickert, Dennis M. ; Ziegler, Fred J.

Author_Institution

Server Group Dev., IBM Corp., Rochester, MN, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

708

Lastpage

716

Abstract

Microprocessors are incredibly complex devices that typically have many non-standard logic, array, and I/O structures. Testing of microprocessors has become an increasingly difficult problem because of these non-standard structures. This paper will discuss the test methodology put in place to test a PowerPC microprocessor which is used in both the AS/400 and RS/6000 computer lines. This microprocessor has a number of features which made test a challenge. These features include partial scan sections of logic, extremely high signal count of nearly 1000 I/O, custom logic designed at the transistor level, and non-scannable arrays not directly accessible from outside the microprocessor

Keywords

application specific integrated circuits; automatic testing; boundary scan testing; built-in self test; design for testability; fault diagnosis; integrated circuit testing; logic testing; microprocessor chips; ASIC logic; DFT; Iddq test; PLL test; PowerPC microprocessor; extremely high signal count; functional test set; high test coverage; logic BIST; nonscannable arrays; partial scan sections of logic; shift register latches; stored patterns; stuck at fault; test methodology; transistor level custom logic; Automatic testing; Costs; Life testing; Logic arrays; Logic design; Logic testing; Microprocessors; Process design; Shift registers; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743215

Filename

743215