Title :
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard
Author :
Dervisoglu, Bulent ; Ricchetti, Mike ; Eldow, B.
Author_Institution :
Synopsys, Mountain View, CA, USA
Abstract :
This paper proposes a framework to help designers understand how to integrate customized design for test features under the guidelines of the 1149.1 standard. The paper begins by discussing the reasoning behind some of the essential features of the IEEE 1149.1 boundary scan standard. Following that, arguments are made for allowing greater flexibility within the standard in order to accommodate design features, that may follow the intent of the standard but not necessarily the letter of its specification. An example of such a feature is to allow I/O cells in which test logic is “shared” with functional logic. The proposed framework for compatibility with the IEEE 1149.1 standard may result in some changes to the current standard. The framework is intended to provide a guideline for additional tools and recommendations to be developed by the IEEE 1149.1 working group and EDA companies in order to help produce testable designs. The framework also helps to explain and understand the ramifications of implementing testability features, which are not compliant with the boundary-scan standard
Keywords :
IEEE standards; VLSI; boundary scan testing; design for testability; integrated circuit testing; logic testing; IEEE 1149.1 boundary-scan standard; IEEE 1149.1 working group; customized design for test features; functional logic; shared I/O-cell structures; test logic; Circuit testing; Digital integrated circuits; Electronic design automation and methodology; Guidelines; Integrated circuit interconnections; Integrated circuit testing; Logic testing; Pins; Standards publication; System testing;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743294