DocumentCode :
252734
Title :
Structure reliability and characterization for FC package w/Embedded Trace coreless Substrate
Author :
Chen, E. ; Lan, A. ; You, J. ; Liao, M.
Author_Institution :
Siliconware Precision Ind. Co., Ltd., Taichung, Taiwan
fYear :
2014
fDate :
3-5 Dec. 2014
Firstpage :
149
Lastpage :
150
Abstract :
In recent years mobile devices are getting more and more involved in to our daily life. With the requirement of IC packages inside mobile devices toward smaller form factor, low cost with high performance, a coreless substrate technology, naming Embedded Trace Substrate (ETS) is developed to meet market requirement and it has been studied in this paper. For an IC package with coreless substrate, warpage performance is a concern comparing to non-coreless substrate package of which has better substrate strength to balance Coefficients of Thermal Expansion (CTE) mismatch from molding compound. A Flip Chip Chip Scale Package (FCCSP) with body size 12×12mm is used as a test vehicle for this study and molding underfill (MUF) structure is selected to reduce package cost of additional underfill material. To evaluate the warpage performance of the ETS coreless substrate, finite element analysis simulation tool is used to compare package warpage for room temperature and high temperature. Also experimental validation of warpage is done by Shadow Moire test equipment. The study matrix includes different molding compound materials, molding compound thicknesses, substrate designs, substrate thicknesses, die thicknesses. By simulation and Shadow Moire measurement results can help the package structure and molding compound material selection that with thicker molding compound thickness, die thickness and substrate thickness have better warpage performance. In addition to warpage, the reliability performance is also evaluated for package under different test conditions such as assembly out time zero, uHAST, TCT and HTST. The evaluation index is Open/Short yield and failure analysis is also done for the O/S failed samples to evaluate failure rate, failure mode and failure locations. In the end, a package structure and bill of material (BOM) selection is finalized to have suitable warpage performance that meets requirement and can also pass reliability criteria.
Keywords :
finite element analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; thermal expansion; ETS coreless substrate; ETS technology; FC package; FCCSP; HTST; IC package requirement; MUF structure; Shadow Moire measurement results; Shadow Moire test equipment; TCT; assembly out time zero; bill-of-material selection; coefficient-of-thermal expansion mismatch; die thickness; embedded trace coreless substrate technology; failure analysis; failure location; failure mode; failure rate; finite element analysis simulation tool; flip chip chip scale package; mobile devices; molding compound; molding compound material selection; molding compound thicknesses; molding underfill structure; open-short yield; package cost reduction; reliability criteria; structure characterization; structure reliability; study matrix; substrate designs; substrate strength; substrate thickness; test vehicle; uHAST; underfill material; warpage performance; Bills of materials; Compounds; Finite element analysis; Reliability; Substrates; Temperature measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
Type :
conf
DOI :
10.1109/EPTC.2014.7028314
Filename :
7028314
Link To Document :
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