Title :
Detection of bridging faults in logic resources of configurable FPGAs using IDDQ
Author :
Zhao, L. ; Walker, D.M.H. ; Lombardi, F.
Author_Institution :
Lucent Technol., Allentown, PA, USA
Abstract :
This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100% coverage of IDDQ-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow IDDQ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for IDDQ-testable bridging faults is achieved in 5 programming phases and 16 IDDQ vectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 IDDQ measurements
Keywords :
automatic test pattern generation; fault simulation; field programmable gate arrays; logic testing; reconfigurable architectures; IDDQ-based test strategy; RAM modes; SRAM based FPGA; Xilinx XC4000 FPGA family; bottom-up test generation approach; bridging faults detection; configurable FPGA; configurable logic blocks; fault coverage; fault model; hierarchical test strategy; internal faults; logic resources; programmability; reconfiguration programming time; reprogrammable FPGA; Circuit faults; Circuit testing; Fault detection; Field programmable gate arrays; Logic programming; Logic testing; Phased arrays; Programmable logic arrays; Read-write memory; System testing;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743302
