DocumentCode :
2528253
Title :
Power-aware testing: The next stage
Author :
Wen, Xiaoqing
Author_Institution :
Kyushu Inst. of Technol., Fukuoka, Japan
fYear :
2012
fDate :
28-31 May 2012
Firstpage :
1
Lastpage :
1
Abstract :
Complex power management circuitry in low-power designs and the excessive gap between functional power and test power have made power-aware testing (DFT and test generation) a must. Although significant progress has been made in the past decade, more is still needed in order to achieve test power safety while maximizing test quality and minimizing test cost. This paper highlights the needs for moving to the next-stage of power-aware testing, primarily characterized by a shift of focus from global test power reduction to pinpoint test power management.
Keywords :
integrated circuit technology; integrated circuit testing; low-power electronics; global test power reduction; pinpoint test power management; power aware testing; Clocks; Discrete Fourier transforms; Europe; Large scale integration; Safety; Testing; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2012 17th IEEE European
Conference_Location :
Annecy
Print_ISBN :
978-1-4673-0696-6
Electronic_ISBN :
978-1-4673-0695-9
Type :
conf
DOI :
10.1109/ETS.2012.6233000
Filename :
6233000
Link To Document :
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