DocumentCode :
252942
Title :
Insulated PdCu wire bond challenges and resolution for HVM robustness
Author :
Siong Chin Teck ; Eu Poh Leng ; Tan Lan Chu ; Ibrahim, M.R. ; Au Ying Kheng ; Yow Kai Yun ; Zhang Xi ; Lee, C. ; Su Dan ; Tok Chee Wei ; Murali, S. ; Lyn, R.
Author_Institution :
Freescale Semicond., Petaling Jaya, Malaysia
fYear :
2014
fDate :
3-5 Dec. 2014
Firstpage :
611
Lastpage :
617
Abstract :
In the recent years, insulated wire bond is getting more attention by packaging technologist as another potential option of cost saving after Cu wire bond conversion due to its flexibility in wire bond without the fear of wire short. This is especially practical for products with very complex and multitier wire bond layout which have higher wire short risk. The process also offers greater flexibility in wire bond layout design which can lead to die size reduction and standardization of substrate / leadframe for cost saving. As the wire has the capability to touch each other without causing electrical short, this feature also has been adopted to generate or enhance the capacitance effect based on device requirement. Insulated wire bond process however has some challenges as compared to the bare wire bond process. With additional organic wire coating as insulation layer, direct contact of 2 metals, i.e. wire and Al pad for IMC formation is not possible. Organic coating needs to be sufficiently removed for inter diffusion of 2 metals. The challenge can be easily observed during post bond formation with wire bond problems such as non stick on lead (NSOL) and short tail if the wire coating is not effectively eliminated through mechanical scrubbing. Ball bond process, with the existence of electrical flame off (EFO) to burn and evaporate organic coating before free air ball (FAB) formation, is a relatively easy process for insulated wire, but thicker insulation coating can result in pointed or irregular FAB formation resulting in non stick on pad problem in some severe cases. This study aims to define an optimum wire bond process and coating material recipe for Tape Ball Grid Array (TBGA) package with first ever attempt at using 18μm PdCu wire size to achieve high volume manufacturing (HVM) capability for 47μm pad pitch. TBGA is well known for its difficulty on post bond formation due to fine pitch lead finger on polyimide flex sitting on top of adhesive - ayers in substrate configuration. The characterization and optimization process involved 4 key factors: capillary, plasma cleaning, wire coating and wire bond parameters. Series of evaluation and DOEs were performed to establish optimized parameter window on each factor in terms of wire bond integrity and bondability. All optimized settings were later integrated and subjected to HVM run. From HVM verification, all wire bond quality requirements were fulfilled. Wire bond MTBA achieved more than 2hrs and successfully passed industrial level package reliability stressings with no electrical failures. In summary, the most challenging 18μm insulated Pd Cu wire bonding process on TBGA package can be made possible through a detailed process characterization and careful consideration of manufacturing performance.
Keywords :
ball grid arrays; lead bonding; palladium compounds; semiconductor device manufacture; DOE; EPO; FAB formation; HVM robustness; PdCu; TBGA package; ball bond process; capacitance effect enhancement; capillary; coating material recipe; cost saving; die size reduction; electrical flame off; free air ball formation; high volume manufacturing capability; industrial level package reliability stressings; insulated wire bond process; insulation layer; leadframe standardization; manufacturing performance; optimization process; organic wire coating; plasma cleaning; process characterization; size 0.18 mum; substrate standardization; tape ball grid array; wire bond layout design; wire bond parameters; Coatings; Plasmas; Rough surfaces; Surface morphology; Surface roughness; Surface treatment; Wires; Cu wire bonding; Insulated Pd coated Cu wire; Tape BGA; ultra fine pitch;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
Type :
conf
DOI :
10.1109/EPTC.2014.7028425
Filename :
7028425
Link To Document :
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