A novel concept for stateless random bit generators in cryptographic applications

A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore easily testable accordingly to what is reported in (Bucci, 2005). Moreover, the generation throughput is automatically adapted to the available noise in the circuit thus guaranteeing the statistical quality (minimum entropy) of the generated bits. To validate the proposed circuit, simulation results on a 0.12mum CMOS process are reported