Title :
Performance and power aware buffered tree construction
Author :
Wang, Yibo ; Cai, Yici ; Hong, Xianlong
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
Abstract :
Power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in power calculation. In this paper, we use accurate delay and power models to construct buffered routing trees with considerations of delay and power optimization. Experimental results show our method can save much of buffer and power dissipation with better solutions
Keywords :
buffer circuits; circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; trees (mathematics); buffered routing trees; buffered tree construction; delay models; integrated circuit design; integrated circuit interconnect; power dissipation; power model; power optimization; Capacitance; Delay effects; Integrated circuit interconnections; Optimization methods; Power dissipation; Power generation; Routing; Simulated annealing; Tree graphs; Wire;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692588
