The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity

We propose an algorithm for reducing the hardware complexity of linear phase FIR digital filters without resorting to an increase in the number of adder steps in the multiplier block adders. We aggressively reduce both the coefficient wordlength and the number of non-zero bits in the filter coefficients so that the adder step can be minimized. The hardware implementation of the coefficients is such that the number of full adders is proportional to the product of the input signal wordlength and the number of adders. That is, in general, the number of full adders is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a 67% and 71% reduction in the number of multiplier block adders and the number of multiplier block full adders respectively. Our technique has been successfully applied to filters with up to 500 taps