A stimulator output stage with capacitor reduction and failure-checking techniques

The use of blocking capacitors in the output stages of implantable stimulators for functional electrical stimulation (FES) applications, is common practice for safety reasons. However, these capacitors tend to dominate the implant volume. This paper describes a stimulator output stage circuit which overcomes this limitation. The circuit features a novel capacitor reduction technique for implant miniaturization, and a simple failure-checking mechanism for enhanced reliability. The approach was verified by simulations in a 0.35 mum CMOS technology