A mesochronous pipeline scheme for high performance low power digital systems

A mesochronous pipeline architecture is described in this paper. Significant performance gains are possible with mesochronous pipeline over conventional pipeline architecture. The clock period in conventional pipeline scheme is proportional to the maximum stage delay while in mesochronous pipelining it is proportional to the maximum delay difference, which means higher clock speeds are possible in the proposed scheme. Also, the clock distribution network is simple and load on it is less in mesochronous approach resulting in significant power savings. An 8times8-bit multiplier using carry-save adder technique has been implemented in conventional and mesochronous pipeline approach using TSMC 180 nm (drawn length 200 nm). The over all power dissipation in mesochronous approach is less than 50% of the power dissipation in conventional approach. In conventional approach, the power dissipation in clock network and pipeline registers is close to 80% of total power dissipation, while in mesochronous approach the logic dissipates more power