Title :
High performance single clock cycle CMOS comparator
Author :
Lam, Hing-Mo ; Tsui, Chi-ying
Author_Institution :
Dept. of Electron. & Electr. Eng., Hong Kong Univ. of Sci. & Technol.
Abstract :
In this paper, a novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm. By doing so, fast dynamic NOR gates are used instead of high-fan-in NAND gates and this results in significant improvement in performance over the traditional design. A test chip has been built in AMS 0.35mum technology and from both post-layout simulation and test chip measurement results, it is shown that the proposed design is 22% faster than the existing fastest single-cycle comparator based on priority-encoder respectively
Keywords :
CMOS integrated circuits; clocks; comparators (circuits); integrated circuit layout; logic design; logic gates; 0.35 micron; AMS technology; CMOS comparator; NAND gates; NOR gates; parallel MSB checking; post-layout simulation; priority-encoding based comparison algorithm; single-cycle comparator; test chip measurement; Adders; Algorithm design and analysis; CMOS logic circuits; CMOS technology; Clocks; Logic design; Logic gates; Partial response channels; Pipeline processing; Testing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692701
