11-ps resolution time interval counter in CMOS ASIC

Author

Klepacki, Kamil ; Szplet, Ryszard

Author_Institution

Dept. of Electron. Eng., Mil. Univ. of Technol., Warsaw, Poland

fYear

2012

fDate

18-21 Sept. 2012

Firstpage

1

Lastpage

5

Abstract

This paper describes a design and test results of time interval counter (TIC), which provides a high resolution of 10.7 ps within a wide measurement range of 1 ms. To achieve these parameters the counting method with a two-stage interpolation within a single clock period is involved. A sub-gate delay resolution is obtained with the aid of the differential delay line technique. To diminish the nonlinearities of conversion and finally to improve the precision of measurement a novel matrix of differential delay lines is proposed. The TIC is implemented as an Application Specific Integrated Circuit (ASIC) in 0.35 μm CMOS process.

Keywords

CMOS integrated circuits; application specific integrated circuits; clocks; counting circuits; delay lines; interpolation; CMOS ASIC process; TIC; application specific integrated circuit; counting method; differential delay line technique; resolution time interval counter; single clock period; size 0.35 mum; subgate delay resolution; time 1 ms; time 11 ps; two-stage interpolation; Clocks; Delay; Delay lines; Generators; Interpolation; Radiation detectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems (ICSES), 2012 International Conference on

Conference_Location

Wroclaw

Print_ISBN

978-1-4673-1710-8

Electronic_ISBN

978-1-4673-1709-2

Type

conf

DOI

10.1109/ICSES.2012.6382227

Filename

6382227