Dynamic sparing and error correction techniques for fault tolerance in nanoscale memory structures

This paper describes a memory organization that supports hierarchical, dynamic fault tolerance mechanisms applicable to heterogeneous CMOS/molecular systems. It has been projected that, in such systems, programmable mapping circuitry becomes necessary when the interface between microscale and nanoscale address lines is formed in a non-deterministic manner. This mapping circuitry may double as a means of implementing more advanced forms of reconfiguration and error correction codes useful in detecting and recovering from runtime faults. Computer simulation is used to estimate the effectiveness of various configurations. Results show that dynamic remapping of spare memory rows allows for improvements in reliability over standard error correction codes.