The miller effect in digital CMOS gates and power consumption analysis

Author

Brzozowski, Ireneusz ; Kos, Andrzej

Author_Institution

Dept. of Electron., AGH-Univ. of Sci. & Technol., Kraków, Poland

fYear

2012

fDate

18-21 Sept. 2012

Firstpage

1

Lastpage

6

Abstract

This paper deals with the Miller Effect occurrence in standard CMOS gates and possibility to take it into considerations during power dissipation analysis. Internal capacitances occurring in MOS transistors give the effect of capacitive coupling between input and output of the gate. It seems that the Miller theorem can be applied in a simplified approach to the analysis of energy and time in static CMOS gates. The main purpose of this paper is to discuss whether the Miller theorem can be effectively used in the analysis of energy and time in CMOS gates. What is the accuracy of such approach and what are the limitations? Theoretical considerations are supplemented by simulations.

Keywords

CMOS logic circuits; MOSFET; logic gates; MOS transistors; Miller effect; Miller theorem; capacitive coupling effect; digital CMOS gates; energy analysis; internal capacitances; power consumption analysis; power dissipation analysis; time analysis; CMOS integrated circuits; Capacitance; Capacitors; Couplings; Inverters; Logic gates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems (ICSES), 2012 International Conference on

Conference_Location

Wroclaw

Print_ISBN

978-1-4673-1710-8

Electronic_ISBN

978-1-4673-1709-2

Type

conf

DOI

10.1109/ICSES.2012.6382242

Filename

6382242