Title :
A low power unified cache architecture providing power and performance flexibility
Author :
Malik, Afzal ; Moyer, Bill ; Cermak, Dan
Author_Institution :
M.CORE Technol. Centre, Motorola Inc., Austin, TX, USA
Abstract :
Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the device´s components. The M.CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with programmable features was added to the M3 core. These features allow the architecture to be optimized based on the application´s requirements. In this paper we focus on the features of the M340 cache sub-system and illustrate the effect on power and performance through benchmark analysis and actual silicon measurements.
Keywords :
cache storage; embedded systems; memory architecture; microprocessor chips; 8 KByte; M.CORE M3 architecture; M340 cache sub-system; benchmark analysis; embedded applications; low power unified cache architecture; microprocessors; set-associative cache; Communication standards; Communication system control; Cyclic redundancy check; Energy consumption; Engines; Lakes; Memory management; Permission; Power measurement; Silicon;
Conference_Titel :
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN :
1-58113-190-9
DOI :
10.1109/LPE.2000.155290