DocumentCode :
2533832
Title :
M-of-N Code Decomposition for Indicating Combinational Logic
Author :
Toms, W.B. ; Edwards, D.A.
Author_Institution :
Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK
fYear :
2010
fDate :
3-6 May 2010
Firstpage :
15
Lastpage :
25
Abstract :
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. In particular, mapping large function blocks into cell-libraries is difficult as decomposing gates introduces new signals which may violate indication. This paper presents a novel method for implementing any m-of-n encoded function block using "bounded gates", where any gate may be decomposed without violating indication. This is achieved by successively decomposing the input encoding into smaller m-of-n codes. The method described in the paper uses algebraic extraction techniques to efficiently determine and quantify potential re-encodings. The results of the synthesis procedure are demonstrated on a range of combinational function blocks.
Keywords :
algebra; logic gates; M-of-N code decomposition; algebraic extraction; bounded gates; cell libraries; combinational function blocks; combinational logic indication; process variation problem; self timed circuits; Asynchronous circuits; Circuit synthesis; Circuit testing; Combinational circuits; Computer science; Cost function; Logic; Network synthesis; Signal synthesis; Timing; Asynchronous Combinational Logic Synthesis; M-of-N Codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on
Conference_Location :
Grenoble
ISSN :
1522-8681
Print_ISBN :
978-0-7695-4032-0
Electronic_ISBN :
1522-8681
Type :
conf
DOI :
10.1109/ASYNC.2010.12
Filename :
5476991
Link To Document :
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