• DocumentCode
    253387
  • Title

    An inventive design of 4*4 bit reversible NS gate

  • Author

    Misra, Neeraj Kumar ; Wairya, Subodh ; Singh, V.K.

  • Author_Institution
    Inst. of Eng. & Technol., Lucknow, India
  • fYear
    2014
  • fDate
    9-11 May 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    The model of computing in which the computational progression is reversible or to some extent time inverting is entitled reversible computing. In the modern epoch reversible logic has materialized as a promising, competent technology comprising its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The conventional gates such as AND, OR, and EXOR are not reversible. Here in this manuscript we put forward a 4*4 reversible gate design called “NSG”. The most noteworthy, considerable attribute of the proposed gate is that it can work individually as a reversible full adder, reversible full subtractor, reversible half adder, and reversible half subtractor. That is now we are capable of implementing reversible full adder, subtractor and reversible half adder, subtractor with a single gate only. The proposition of this meticulous manuscript is a design a parity preservation property using NS Gate.
  • Keywords
    logic design; logic gates; NSG; computational progression; reversible NS gate; reversible computing; reversible full adder; reversible full subtractor; reversible gate design; reversible half adder; reversible half subtractor; reversible logic; Clocks; Computational modeling; Delays; Logic gates; Quantum computing; Table lookup; Constant Input; Garbage Output; Low-Power VLSI etc.; Reversible Logic Gate; Reversible Logic circuit;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Recent Advances and Innovations in Engineering (ICRAIE), 2014
  • Conference_Location
    Jaipur
  • Print_ISBN
    978-1-4799-4041-7
  • Type

    conf

  • DOI
    10.1109/ICRAIE.2014.6909323
  • Filename
    6909323