Title :
On single electron technology full adders
Author :
Sulieman, Mawahib ; Beiu, Valeriu
Author_Institution :
Sch. of EE&CS, Washington State Univ., Pullman, WA, USA
Abstract :
This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper provides a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This can allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, is described and compared with the other SET FAs.
Keywords :
adders; logic design; logic gates; single electron transistors; threshold logic; capacitive single electron technology threshold logic gates; full adder design; power dissipation; process delay; process variation sensitivity; Adders; Birth disorders; Capacitors; Circuits; Clocks; Delay estimation; Electrons; Inverters; Logic devices; Power dissipation;
Conference_Titel :
Nanotechnology, 2004. 4th IEEE Conference on
Print_ISBN :
0-7803-8536-5
DOI :
10.1109/NANO.2004.1392337
