DocumentCode :
2534191
Title :
A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization
Author :
Banerjee, S. ; Mathew, J. ; Pradhan, D.K. ; Mohanty, S.P. ; Ciesielski, M.
Author_Institution :
Univ. of Bristol, Bristol, UK
fYear :
2010
fDate :
20-22 Dec. 2010
Firstpage :
71
Lastpage :
76
Abstract :
Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano - CMOS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage current during behavioral synthesis. It uses TED (Taylor Expansion Diagram) for generating optimized DFG (Data Flow Graph). Once DFG is obtained, it selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of behavioral synthesis benchmarks for 45 nm process show 30% to 70% reduction in leakage current compared to the results obtained by a conventional optimization flow.
Keywords :
CMOS integrated circuits; data flow graphs; integrated circuit modelling; optimisation; RTL leakage optimization; Taylor expansion diagram; behavioral synthesis benchmarks; data flow graph; exponential behavior; gate-oxide leakage current; nano-CMOS circuit; technology scaling; temperature scaling; wavelength 45 nm; CMOS integrated circuits; Delay; Leakage current; Libraries; Logic gates; Optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic System Design (ISED), 2010 International Symposium on
Conference_Location :
Bhubaneswar
Print_ISBN :
978-1-4244-8979-4
Electronic_ISBN :
978-0-7695-4294-2
Type :
conf
DOI :
10.1109/ISED.2010.22
Filename :
5715152
Link To Document :
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