Abstract :
Body biasing, inverter topology, and charge restoring techniques for subthreshold domino circuits are evaluated for speed, energy, and noise immunity. Forward body-biasing minimizes energy, whereas dynamic body-biasing, effective in minimizing leakage, exacerbates clock feedthrough. At low frequencies, the traditional "keeper" scheme is energy efficient and solves problems related to leakage and charge-sharing. Pre-charging internal nodes minimizes charge-sharing but increases delay and power, particularly for large fan-in gates. For these gates at moderate frequencies, the two methods together strike a judicious balance among power, delay, and robustness
Keywords :
CMOS logic circuits; logic gates; CMOS circuits; body biasing; charge restoring; fan-in gates; inverter topology; noise immunity; subthreshold domino circuits; Circuit noise; Circuit topology; Clocks; Delay; Energy efficiency; Frequency; Immune system; Inverters; Low-frequency noise; Noise robustness;