• DocumentCode
    2536688
  • Title

    One-two-one track asynchronous FIFO

  • Author

    Varshavsky, Victor I. ; Marakhovsky, Vyacheslav B.

  • Author_Institution
    Univ. of Aizu, Fukushima, Japan
  • fYear
    1998
  • fDate
    24-27 Nov 1998
  • Firstpage
    743
  • Lastpage
    746
  • Abstract
    A novel logic circuit for a very fast one-two-one-track register pipeline is suggested. Its control logic provides the maximum possible throughput. This FIFO is intended for use in the Line Interface Module (LIM) implementing the direct ATM-over-fiber transport mechanism
  • Keywords
    asynchronous circuits; buffer storage; pipeline processing; shift registers; asynchronous FIFO; control logic; direct ATM-over-fiber transport mechanism; line interface module; logic circuit; one-two-one-track register pipeline; very fast register pipeline; Circuits; Frequency synchronization; Latches; Logic; Pipelines; Propagation delay; Prototypes; Registers; Throughput; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
  • Conference_Location
    Chiangmai
  • Print_ISBN
    0-7803-5146-0
  • Type

    conf

  • DOI
    10.1109/APCCAS.1998.743928
  • Filename
    743928
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2536688