Title :
Reconfiguration of folded torus PE networks for fault tolerant WSI implementations
Author_Institution :
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
Abstract :
This paper describes the reconfiguration of torus networks for fault tolerant WSI implementations, in which the reconfiguration of interconnections is especially emphasized. The number of tracks in each channel required for the reconfiguration is estimated, and a two-step approach, which includes the construction of compensation paths followed by their modifications, for the reconfiguration with a reduced number of tracks is proposed
Keywords :
fault tolerant computing; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; microprocessor chips; multiprocessor interconnection networks; network routing; parallel architectures; reconfigurable architectures; wafer-scale integration; PE array; compensation paths; fault tolerant WSI implementations; folded torus PE networks; interconnections; processing elements; reconfiguration; Computer architecture; Electronic mail; Fault tolerance; Information science; Paper technology; Parallel processing; Routing; Switches; Very large scale integration; Wiring;
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
DOI :
10.1109/APCCAS.1998.743940
