Low-power mechanism with power block management

In this paper, a low power mechanism with power block management is proposed to reduce the power consumption in DSP chips. Because the digital signal processing (DSP) chips use many functional units in the data-path to achieve parallel processing, the unnecessary functional units are also executed simultaneously, and they dissipate the power. In the paper, we classify the types of instruction sets based on their data flow in the DSP to generate the control signals which active the necessary units in their data-path. The mechanism is called power block management (PBM). We employ particular guarded circuits in the different situations to avoid the actions of unnecessary functional units so as to reduce the power dissipation. The experimental results show that the power consumption can be saved about 14% at the cost of less than 2.7% area increment