A study of floating-point architectures for pipelined RISC processors

To achieve an increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs) are used. However, there is a need to analyze the suitability of floating-point architectures for high-speed or low power applications. In this research, different system-level architectures and operational algorithms of FPUs were implemented using 0.25mum CMOS standard cells. Fair comparison of design metrics in terms of speed, area and power consumption were made and analyzed for each design. Simulation results show that architectures with an independent pipeline for division perform better in terms of speed while combined pipelines consume the least power. Also, architectures with a combined pipeline for addition and multiplication and an independent pipeline for division occupy the smallest layout area and, in general, show the best performance in all three metrics