Second order dynamic element matching technique for low oversampling delta sigma ADC

There has been an increased interest in design of broadband (data rate >1MSPS) delta sigma ADCs with over-sampling ratios (OSR) as low as four. Most of these designs are switched capacitor based and use internal multi-bit DACs. With the widely used first order dynamic element matching, the SNDR of these converters is limited by the inherent capacitor matching. We propose a modified second order dynamic element matching technique to alleviate this problem for broadband ADCs, which target a SNDR greater than 100dB