Design of a 4-bit programmable delay with TDC-based BIST for use in serial data links

Time mode signal processing (TMSP) in general is defined as the manipulation of sampled analog signal information using time difference variable. TMSP allows one to implement analog signal processing functions using the most basic element available, namely, propagation delay. A time to digital converter (TDC) is used to convert the time difference between two edges of two signals into a sequence of digital numbers. TDCs have been extensively used in designing laser range finders, all digital phase locked loops (ADPLL), frequency synthesizers, analog to digital converters (ADC), SerDes, etc. This paper proposes a new approach that utilizes a TDC for detection of potential stuck-at faults in a 4-bit programmable delay to be used in designing a time mode SerDes. Moreover, the proposed approach suggests that, when any circuit needs to delay a certain signal, it can be confirmed whether the amount of delay is correctly enforced by utilizing a TDC module and translating the difference between the main signal and the delayed version of the signal into a sequence of bits. Then, one can observe if the generated bits correspond to a correct operation of the circuitry in charge of delaying the main signal.