DocumentCode :
2545446
Title :
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
Author :
Ying Zhou ; Zhuo Li ; Yuxin Tian ; Weiping Shi ; Liu, F.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX
fYear :
2007
fDate :
23-26 Jan. 2007
Firstpage :
450
Lastpage :
455
Abstract :
Even with the wide adaptation of resolution enhancement techniques in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing layout parasitic extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis. Our simulation shows that the RC parasitics extracted from perfect GDS-II geometry can be as much as 20% different from those extracted from the post litho/etching simulation geometry. This paper presents a new LPE methodology and related fast algorithms for interconnect parasitic extraction under photolithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient.
Keywords :
integrated circuit interconnections; photolithography; semiconductor process modelling; design flow; fast algorithms; interconnect parasitics extraction; layout parasitic extraction; photolithography effects; Computational geometry; Etching; Geometrical optics; Inductance; Integrated circuit interconnections; Lithography; Optical distortion; Shape; Solid modeling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
1-4244-0629-3
Type :
conf
DOI :
10.1109/ASPDAC.2007.358027
Filename :
4196073
Link To Document :
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