• DocumentCode
    254648
  • Title

    A hybrid mapreduce model for prolog

  • Author

    Corte-Real, J. ; Dutra, I. ; Rocha, R.

  • Author_Institution
    Fac. of Sci., Univ. of Porto, Porto, Portugal
  • fYear
    2014
  • fDate
    10-12 Dec. 2014
  • Firstpage
    340
  • Lastpage
    343
  • Abstract
    Interest in the Map Reduce programming model has been rekindled by Google in the past 10 years; its popularity is mostly due to the convenient abstraction for parallelization details this framework provides. State-of-the-art systems such as Google´s, Hadoop or SAGA often provide added features like a distributed file system, fault tolerance mechanisms, data redundancy and portability to the basic Map Reduce framework. However, these features pose an additional overhead in terms of system performance. In this work, we present a Map Reduce design for Prolog which can potentially take advantage of hybrid parallel environments; this combination allies the easy declarative syntax of logic programming with its suitability to represent and handle multi-relational data due to its first order logic basis. Map Reduce for Prolog addresses efficiency issues by performing load balancing on data with different granularity and allowing for parallelization in shared memory, as well as across machines. In an era where multicore processors have become common, taking advantage of a cluster´s full capabilities requires the hybrid use of parallelism.
  • Keywords
    PROLOG; data handling; logic programming; parallel programming; resource allocation; shared memory systems; Google; Hadoop; Prolog; SAGA; data redundancy; declarative syntax; distributed file system; fault tolerance mechanisms; first order logic basis; hybrid MapReduce programming model; load balancing; logic programming; multicore processors; multirelational data handling; portability; shared memory; Computer architecture; Google; Logic programming; Parallel processing; Process control; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits (ISIC), 2014 14th International Symposium on
  • Conference_Location
    Singapore
  • Type

    conf

  • DOI
    10.1109/ISICIR.2014.7029555
  • Filename
    7029555