A low-cost architecture for DWT filter banks in RNS applications

This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multipliers of the RNS-based filter banks are simplified using the low-cost moduli set (2ⁿ -1, 2ⁿ, 2ⁿ+1) and 6-bit dyadic-fraction filter coefficients. The FPGA synthesis results show that the proposed RNS-based filters operate 28% faster than the initial filter banks operated by binary arithmetic. Another noteworthy result is that the proposed RNS-based filter bank require less area compared to the initial filter bank. It confirms that using the proposed architecture for RNS-based filter banks has saved on the hardware complexity and the system area requirement.