Fault-tolerant embedded control systems for unreliable hardware

Past years have seen intense research on reliability techniques for error detection recovery at various levels ranging from circuit level up to architectural level or even software level. In such scenarios, affordable techniques for error correction usually imply a timing penalty, e.g., check-pointing usually requires to repeat some part of the computation, which imposes a higher computation time. This can be problematic for real-time embedded control applications especially in the presence of intermittent hardware faults, for which delays due to re-computation are repeatedly encountered with high repetition rate. In this work, we investigate a setting where the control loops are executed on an unreliable embedded platform that may suffer from such intermittent faults. First, we characterize the impact of intermittent faults in the hardware by using an intermittent bit-flip fault model and RTL level error effect simulation. Subsequently, we look at novel fault-tolerant control algorithms that guarantee stability of the loops even in presence of repeating timing errors due to the error recovery of the unreliable hardware.