Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner

Sequence alignment has attracted many attentions from various aspects of research domains, including architectures, algorithms, and applications. However, due to the tremendous computing and engineering efforts, it is reasonable and acceptable to reduce the sensitivity of the methodology, in order to maintain a satisfying speed. In this paper, we propose a PC-FPGA hybrid system to evaluate and analyze the trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner. With respect to the reconfiguration and adaptation abilities, the FPGA board is able to provide fast prototyping system with different configurations. Experimental results on the FPGA prototype depicts the quantitative analysis of the trade-offs between the sensitivity and the speed.