A compact hardware implementation of SM3

With mobile and wireless devices becoming pervasive, the low-cost hardware implementations of security functions are being desired. A compact hardware implementation of SM3 hash algorithm is presented in this paper. A SRAM is used to do message expansion function instead of shift registers which are used in common hardware implementations, and the computation units are saved as much as possible. In addition, the values of A~H and V0~V7 registers are updated in serial shift way when they are initialized and updated. Compared to traditional designs, the store resources for message expansion function can be shared with other modules to reduce the cost of a system. The Synopsys´ DC synthesis results show that the area of the compact SM3 is approximate 9822 GEs while its throughput can be as high as 276 Mbps. If the SRAM can be shared with other modules, only 7806 GEs are additional required to add the SM3 hardware module in the system. The compact architecture can be accommodated to resource-constrained systems for its advantages of low-cost and low-power.