Single fault masking logic designs with error correcting codes

Author

Lo, Jien-Chung

Author_Institution

Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

fYear

1995

fDate

13-15 Nov 1995

Firstpage

296

Lastpage

304

Abstract

Triple modular redundancy (TMR) has been the most popular method in reliable logic designs due to a single fault masking capability. However, the reliability of a TMR design can be improved only by enhancing the reliabilities of the components. This paper examines the use of error correcting codes in reliable logic design. The goal is to provide an equivalent single fault masking capability as that of TMR scheme. Further, by reducing the level of hardware redundancy, a higher reliability can be achieved. Design examples are given to illustrate the key issues in single fault masking logic designs with error correcting codes. Reliabilities of different single fault masking carry lookahead adder designs are also examined

Keywords

adders; carry logic; error correction codes; fault diagnosis; logic design; logic testing; redundancy; TMR design; carry lookahead adder designs; error correcting codes; hardware redundancy; logic designs; single fault masking; triple modular redundancy; Adders; Circuit faults; Electrical fault detection; Error correction; Error correction codes; Fault detection; Hardware; Logic circuits; Logic design; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,

Conference_Location

Lafayette, LA

ISSN

1550-5774

Print_ISBN

0-8186-7107-6

Type

conf

DOI

10.1109/DFTVS.1995.476964

Filename

476964